Variables de interés en el estudio de los efectos del ejercicio excéntrico sobre el rendimiento deportivo. Revisión bibliográfica

El ejercicio excéntrico, especialmente si implica un importante grado de estiramiento del músculo contraído, se asocia a dolor muscular tardío o “agujetas” que aparece en regiones musculares sometidas a esfuerzo, horas después de la finalización del ejercicio, alcanzando su máxima intensidad, generalmente, entre las 24 y las 72 horas. Normalmente se acompaña de una ligera tumefacción, disminución del rango de movimiento articular, rigidez y pérdida de fuerza. Una de las características principales de las “agujetas” es la hipersensibilidad, la cual se manifiesta debido a una reducción del umbral de dolor a la estimulación mecánica, de tal manera que estímulos normalmente inocuos (como una ligera presión en la zona afectada) desencadenan sensación dolorosa. A este fenómeno se le denomina alodinia mecánica. Durante los últimos tiempos, ha sido considerable el interés suscitado en la comunidad científica por las lesiones que se producen en los músculos como consecuencia de las contracciones musculares excéntricas. Este interés obedece, en parte, a los efectos negativos que puede tener el daño muscular causado por las contracciones musculares excéntricas sobre el rendimiento deportiv

A New Architectural Survey and some Basic Assumptions for the Study of Priory Church of Carmona

La iglesia prioral de Santa María de Carmona es uno de los ejemplares más importantes surgidos al calor de la gran obra gótica de la catedral de Sevilla. Esta monumental fábrica se erigió a lo largo del último cuarto del siglo XV y de la primera mitad del XVI a través de dos etapas sensiblemente diferenciadas. En el presente trabajo se revisa su historia constructiva y se reflexiona sobre la naturaleza y transformaciones del proyecto gótico, basándose en el análisis de la obra conservada y de un nuevo plano general, ejecutado en el marco de una investigación general sobre el edificio tardogótico.The priory church of Santa Maria de Carmona is one of the most important examples forged in the heat of the great Gothic work of the Cathedral of Seville. This monumental building was erected during the last quarter of the fifteenth century and the first half of the sixteenth through two substantially different stages. In this paper, we review their constructive history and reflect on the nature and transformations of Gothic project, based on the analysis of the work preserved and a new plan view, implemented as a part of a general research on the late Gothic building.Ministerio de Economía y Competitividad (España) HAR2012-3515

A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems

Dynamically reconfigurable hardware is a promising technology that combines in the same device both the high performance and the flexibility that many recent applications demand. However, one of its main drawbacks is the reconfiguration overhead, which involves important delays in the task execution, usually in the order of hundreds of milliseconds, as well as high energy consumption. One of the most powerful ways to tackle this problem is configuration reuse, since reusing a task does not involve any reconfiguration overhead. In this paper we propose a configuration replacement policy for reconfigurable systems that maximizes task reuse in highly dynamic environments. We have integrated this policy in an external taskgraph execution manager that applies task prefetch by loading and executing the tasks as soon as possible (ASAP). However, we have also modified this ASAP technique in order to make the replacements more flexible, by taking into account the mobility of the tasks and delaying some of the reconfigurations. In addition, this replacement policy is a hybrid design-time/run-time approach, which performs the bulk of the computations at design time in order to save run-time computations. Our results illustrate that the proposed strategy outperforms other state-ofthe-art replacement policies in terms of reuse rates and achieves near-optimal reconfiguration overhead reductions. In addition, by performing the bulk of the computations at design time, we reduce the execution time of the replacement technique by 10 times with respect to an equivalent purely run-time one

A Study of the Robustness Against SEUs of Digital Circuits Implemented with FPGA DSPs

In this paper we present an experimental validation of the reliability increase of digital circuits implemented in XilinxTMFPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device. For this purpose, we have used a fault-injection platform developed by our research group, NESSY [1]. The presented experiments demonstrate that the probability of occurrence of a SEU effect is similar both in the circuits implemented with and without using embedded DSPs. However, the former are more efficient in terms of area usage, which leads to a decrease in the probability of a SEU occurrence

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

This paper addresses the problem of reliability and makespan optimization of hardware task graphs in reconfigurable platforms by applying fault tolerance (FT) techniques to the running tasks based on the exploration of the Pareto set of solutions. In the presented solution, in contrast to the existing approaches in the literature, task graph scheduling, tasks parallelism, reconfiguration delay, and FT requirements are taken into account altogether. This paper first presents a model for hardware task graphs, task prefetch and scheduling, reconfigurable computer, and a fault model for reliability. Then, a mathematical model of an integer nonlinear multi-objective optimization problem is presented for improving the FT of hardware task graphs, scheduled in partially reconfigurable platforms. Experimental results show the positive impacts of choosing the FT techniques selected by the proposed solution, which is named Pareto-based. Thus, in comparison to nonfault-tolerant designs or other state-of-the-art FT approaches, without increasing makespan, about 850% mean time to failure (MTTF) improvement is achieved and, without degrading reliability, makespan is improved by 25%. In addition, experiments in fault-varying environments have demonstrated that the presented approach outperforms the existing state-of-the-art adaptive FT techniques in terms of both MTTF and makespan

A Study of the Robustness Against SEUs of Digital Circuits Implemented with FPGA DSPs

In this paper we present an experimental validation of the reliability increase of digital circuits implemented in XilinxTMFPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device. For this purpose, we have used a fault-injection platform developed by our research group, NESSY [1]. The presented experiments demonstrate that the probability of occurrence of a SEU effect is similar both in the circuits implemented with and without using embedded DSPs. However, the former are more efficient in terms of area usage, which leads to a decrease in the probability of a SEU occurrence

An Approach to Manage Reconfigurations and Reduce Area Cost in Hard Real-Time Reconfigurable Systems

This article presents a methodology to build real-time reconfigurable systems that ensure that all the temporal constraints of a set of applications are met, while optimizing the utilization of the available reconfigurable resources. Starting from a static platform that meets all the real-time deadlines, our approach takes advantage of run-time reconfiguration in order to reduce the area needed while guaranteeing that all the deadlines are still met. This goal is achieved by identifying which tasks must be always ready for execution in order to meet the deadlines, and by means of a methodology that also allows reducing the area requirements